1. Field of the Invention
The present invention generally relates to clock and data recovery, and more particularly to a half-rate clock and data recovery circuit.
2. Description of Related Art
Clock and data recovery (CDR) is a crucial building block adopted in a receiver of a wireline communication system, such as an optical-fiber or a serial-link system. Jitter tolerance and jitter transfer function are two important parameters to characterize a CDR circuit. The jitter tolerance is defined as the maximum amplitude of a sinusoidal jitter that is tolerated without increasing a bit error rate (BER). The jitter transfer function is defined as an output jitter divided by an input jitter varying at difference rates. In order to enhance the jitter tolerance of a CDR circuit, a loop bandwidth needs to be increased. The increased loop bandwidth, nevertheless, degrades the jitter transfer function. Therefore, a compromise needs to be reached between the jitter tolerance and the jitter transfer function in a conventional CDR circuit.
For the foregoing reason, a need has thus arisen to propose a novel CDR circuit with enhanced jitter tolerance without sacrificing the jitter transfer function.